1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors with a source and drain formed by solid phase diffusion
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation, and then the implanted dopant is driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
There are several drawbacks to using ion implantation. For instance, a phenomena called xe2x80x9cchannelingxe2x80x9d may occur when the ion beam which implants the dopant is closely aligned with the crystal lattice of the silicon. When channeling occurs, the dopant is initially implanted deep beneath the top surface of the substrate, but then as implantation continues the substrate surface becomes amorphous and less channeling occurs. Unfortunately, the depth of the channeled dopant is difficult to control. Channeling can be avoided by taking the substrate (typically, at an angle of 7xc2x0) with respect to the ion beam, but implanting off-axis can cause asymmetric doping of the source and drain. Another drawback of ion implantation is random scattering of the implanted dopant. The random scattering results in a small portion of the implanted regions, measured as the lateral xe2x80x9cstraggle,xe2x80x9d being disposed beneath the mask . A further drawback of ion implantation is that the concentration (or doping profile) of the implanted dopant typically forms a gaussian distribution along the vertical axis in which the peak concentration is substantially below the top surface of the substrate, and subsequent high-temperature processing causes the dopant to diffuse further into the substrate.
A strategy for enhancing submicron IGFET performance is to form shallow channel junctions on the order of 100 to 1500 microns deep in order to improve current drive and reduce off-state leakage current. However, even as ion implantation energies are scaled down to the range of 5 to 10 kiloelectron-volts and smaller, it remains difficult or impossible to form well-controlled shallow junctions using conventional semiconductor implantation equipment for the reasons mentioned above.
As an alternative to ion implantation, the introduction of source/drain doping by solid phase diffusion is known in the art. Doped layers such as polysilicon, polycide, silicon dioxide, borosilicate glass (BSG) and phosphosilicate glass (PSG) have been used as a diffusion source for source/drain regions that are self-aligned with the gate. A primary advantage of solid phase diffusion is that the peak dopant concentration in the substrate can occur in close proximity to the top surface of the substrate, thereby providing shallow channel junctions even after bigh-temperature processing.
A problem encountered in P-channel devices with polysilicon gates containing a high concentration of boron is that when a thin gate oxide is used, high temperature steps may cause unwanted boron penetration into the gate oxide, or further, into the underlying channel region. For instance, boron will penetrate thin gate oxides during a 900xc2x0 C. post-implant anneal in nitrogen. Furthermore, the presence of fluorine in the gate oxide worsens the boron penetration problem. Such fluorine can be introduced into the gate oxide if boron difluoride (BF2) is the implant species. Boron penetration can cause a positive shift in threshold voltage (VT) and increase subthreshold swing (St). It can also cause other undesirable effects such as increased electron trapping, decreased low-field hole mobility, and decreased drive current due to polysilicon depletion (insufficient polysilicon doping) at the gate oxde interface (which increases the effective thickness of the gate oxide).
Unfortunately, since solid phase diffusion normally requires temperatures of 900xc2x0 C. or more, the resultant boron penetration may be sufficiently large to substantially degrade device performance.
Accordingly, a need exists for a method of making an IGFET that realizes the advantages of solid phase diffusion while reducing or eliminating boron penetration.
An object of the invention is to provide a method of making an IGFET using solid phase diffusion to dope the source and drain without diffusing an appreciable amount of any dopant from the gate into the substrate. This is accomplished by providing essentially all doping for the gate, source and drain using a single solid phase diffusion step. In this manner, when solid phase diffusion occurs, the gate is essentially devoid of preexisting dopants that might otherwise diffuse into the substrate.
In accordance with one aspect of the invention, a method of making an IGFET includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region.
Preferably, the gate is polysilicon, the dopant is boron or boron species, the dopant provides essentially all P-type doping for the gate, source and drain, and essentially none of the dopant diffuses from the gate into the substrate. It is also preferred that the diffusion source layer is polysilicon doped in situ to saturation as it is deposited on the insulating layer, the insulating layer and gate insulator are silicon dioxde, and the diffusion source layer is removed after solid phase diffusion occurs.
Advantageously, the invention is well-suited for making P-channel enhancement-mode IGFETs with shallow channel junctions while reducing or eliminating boron penetration from the gate into the substrate.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.